Complementary metal oxide semiconductor (CMOS) is a dominant technology in semiconductor device manufacture. A CMOS device includes both n-channel (NMOS) and p-channel (PMOS) transistors. In CMOS technology, both kinds of transistors are used in a complementary way to form a current gate that forms an effective means of electrical control. Advantageously, CMOS transistors use very little power when not switching from one state to another.
It is known that the mobility of carriers is dependent on a number of factors, including the surface plane of a wafer. Conventional silicon substrates typically have a surface oriented on the (100) crystal plane. In this plane, the mobility of electrons is higher than in other crystal planes, and therefore, the source-drain current of an n-channel FET formed on the semiconductor substrate having the (100) plane provides the largest current. However, the mobility of holes is not optimized in the (100) plane, and therefore, the source-drain current of a p-channel FET formed on the semiconductor substrate having the (100) plane is inevitably small. The p-channel FET therefore fails to have desirable characteristics, even though the n-channel FET exhibits good characteristics. Hole mobility could be enhanced, especially at high electric fields, if p-channel FETs were formed on the (110) plane.
U.S. Pat. No. 5,384,473, which is incorporated herein by reference, discloses a semiconductor body having element formation surfaces with different orientations. The semiconductor body is constructed in such a manner that a first semiconductor substrate of the (100) plane is laminated to a second semiconductor substrate of the (110) plane. At least one opening is made in the first semiconductor substrate to expose the second semiconductor substrate. An n-channel transistor can be formed in the first semiconductor substrate while a p-channel transistor is formed in the second semiconductor substrate.
The paper by Yang et al., entitled High Performance CMOS Fabricated on Hybrid Substrate With Different Crystal Orientations,” 2003 IEDM, pp. 18.7.1-18.7.4, which is incorporated herein by reference, discloses a structure and technology for high performance CMOS using hybrid silicon substrates with different crystal orientations through wafer bonding and selective epitaxy. This type of mixed orientation substrate (MOS) provides a technology to boost the PMOS performance by using a (110) substrate while maintaining the NMOS performance by using (100) substrate. One of the challenges with a mixed orientation substrate lies in isolating the (110) portions of the substrate from the (100) portions of the substrate and at the same time to make the good alignment with the shallow trench isolation (STI) later on, especially for the technologies below 45 nm.